MAX15015EVKIT【PDF 21/26 页】EVAL KIT FOR MAX15015

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1A, 4.5V to 40V Input Buck Converters with

50mA Auxiliary LDO Regulators

The error amplifier gain between f P2 and f P3 is approxi-

mately equal to R5 / (R6 || R3).

The ESR zero frequency f ZESR might not be very much

higher than the double-pole frequency f LC , therefore

the value of R5 can be calculated as:

V IN_LDO

IN_LDO

LDO_OUT

R 5 =

R 3 × R 6

R 3 + R 6

×

f C 2

G MOD _ DC × f LC 2

MAX15014–

R1

C7 can still be calculated as:

MAX15017

SET_LDO

C 7 =

1

0 . 5 × 2 π × R 5 × f LC

SGND

R2

f P3 is set at 5xf C . Therefore, C8 is calculated as:

C 8 =

C 7

2 π × C 7 × R 5 × f P 3 ? 1

Figure 5. Setting the Output Voltage Using a Resistive Divider

Connect CT to LDO_OUT to select the internally fixed

Setting the LDO Linear

Regulator Output Voltage

The MAX15014–MAX15017 LDO regulator features Dual

Mode ? operation: it can operate in either a preset voltage

mode or an adjustable mode. In preset voltage mode,

internal trimmed feedback resistors set the internal linear

regulator to 3.3V or 5V (see the Selector Guide). Select

preset voltage mode by connecting SET_LDO to ground.

In adjustable mode, select an output voltage between

1.5V and 11V using two external resistors connected as a

voltage-divider to SET_LDO (see Figure 5). Set the output

voltage using the following equation:

timeout period. C CT must be low-leakage-type capaci-

tor. Ceramic capacitors are recommended; do not use

capacitors lower than 200pF to avoid the influence of

parasitic capacitances.

Capacitor Selection and

Regulator Stability

For stable operation over the full temperature range and

with load currents up to 50mA, use a 10μF (min) output

capacitor (C LDO_OUT ) with a maximum ESR of 0.4 ? . To

reduce noise and improve load-transient response, sta-

bility, and power-supply rejection, use larger output

capacitor values. Some ceramic dielectrics such as Z5U

V OUT = V SET _ LDO ? 1 +

R 2 ?

?

?

R 1 ?

?

and Y5V exhibit very large capacitance and ESR varia-

tion with temperature and are not recommended. With

X7R or X5R dielectrics, 15μF should be sufficient for

where V SET_LDO = 1.241V and the recommended value

for R2 is around 50k ? .

Setting the RESET Timeout Delay

The RESET timeout period is adjustable to accommo-

date a variety of μP applications. Adjust the RESET

timeout period by connecting a capacitor (C CT )

between CT and SGND.

operation over their rated temperature range. For higher-

ESR tantalum capacitors (up to 1 ? ), use 22μF or more to

maintain stability. To improve power-supply rejection

and transient response use a minimum 0.1μF capacitor

between IN_LDO and SGND.

Power Dissipation

The MAX15014–MAX15017 are available in a thermally

enhanced package and can dissipate up to 2.86W at

T A = +70°C. When the die temperature reaches

t RP =

C CT × V CT ? TH

I CT ? THQ

+160°C, the part shuts down and is allowed to cool.

After the die cools by 20°C, the device restarts with a

soft-start. The power dissipated in the device is the

where V CT-TH = delay comparator threshold (rising) =

1.241V (typ), I CT-THQ = CT charge current = 2 x 10 -6 A

(typ), t RP is in seconds and C CT is in Farads.

Dual Mode is a trademark of Maxim Integrated Products, Inc.

sum of the power dissipated in the LDO, power dissi-

pated from supply current (P Q ), transition losses due to

switching the internal power MOSFET (P SW ), and the

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